Field of the Invention
The invention relates to chip packaging technology, and in particular to stacked chip packages and methods for forming the same.
Description of the Related Art
In general, after a chip package is formed, the chip package is bonded onto a packaging component, such as an interposer or a printed circuit board (PCB). External conducting structures are formed between the chip package and the packaging component. Conducting pads in the chip package are electrically connected to circuits on the packaging component through the external conducting structures, such that a stacked chip package is formed.
However, the external conducting structures increase the entire size of the stacked chip package. As a result, it is difficult to further decrease the size of stacked chip packages made therefrom.
Thus, there exists a need in the art for development of a stacked chip package and methods for forming the same capable of mitigating or eliminating the aforementioned problems.